 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| mpc603/d (motorola order number) 6/94 rev 3 mpr603tsu-03 (ibm order number) used by motorola under license from ibm corp. powerpc, powerpc architecture, power architecture, powerpc 603, and powerpc 601 are trademarks of international business machines corp. this document contains information on a new product under development. speci?ations and information herein are subject to change without notice. motorola inc. 1994 portions hereof international business machines corp. 1991?994
2 powerpc 603 risc microprocessor technical summary part 1 powerpc 603 microprocessor overview this section describes the features of the 603, provides a block diagram showing the major functional units, and gives an overview of how the 603 operates. the 603 is the ?st low-power implementation of the powerpc microprocessor family of reduced instruction set computer (risc) microprocessors. the 603 implements the 32-bit portion of the powerpc architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and ?ating-point data types of 32 and 64 bits. for 64-bit powerpc microprocessors, the powerpc architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. the 603 provides four software controllable power-saving modes. three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. the fourth is a dynamic power management mode that causes the functional units in the 603 to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. the 603 is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can execute out of order for increased performance; however, the 603 makes completion appear sequential. the 603 integrates ?e execution units?n integer unit (iu), a ?ating-point unit (fpu), a branch processing unit (bpu), a load/store unit (lsu), and a system register unit (sru). the ability to execute ?e instructions in parallel and the use of simple instructions with rapid execution times yield high ef?iency and throughput for 603-based systems. most integer instructions execute in one clock cycle. the fpu is pipelined so a single-precision multiply-add instruction can be issued every clock cycle. the 603 provides independent on-chip, 8-kbyte, two-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (mmus). the mmus contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (dtlb and itlb) that provide support for demand-paged virtual memory address translation and variable-sized block translation. the tlbs and caches use a least recently used (lru) replacement algorithm. the 603 also supports block address translation through the use of two independent instruction and data block address translation (ibat and dbat) arrays of four entries each. effective addresses are compared simultaneously with all four entries in the bat array during block translation. in accordance with the powerpc architecture, if an effective address hits in both the tlb and bat array, the bat translation takes priority. the 603 has a selectable 32- or 64-bit data bus and a 32-bit address bus. the 603 interface protocol allows multiple masters to compete for system resources through a central external arbiter. the 603 provides a three-state coherency protocol that supports the exclusive, modi?d, and invalid cache states. this protocol is a compatible subset of the mesi (modi?d/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. the 603 supports single-beat and burst data transfers for memory accesses; it also supports both memory-mapped i/o and direct-store interface addressing. the 603 uses an advanced, 3.3-v cmos process technology and maintains full interface compatibility with ttl devices. 1.1 powerpc 603 microprocessor features this section describes details of the 603 s implementation of the powerpc architecture. major features of the 603 are as follows: high-performance, superscalar microprocessor as many as three instructions issued and retired per clock as many as ?e instructions in execution per clock powerpc 603 risc microprocessor technical summary 3 single-cycle execution for most instructions pipelined fpu for all single-precision and most double-precision operations five independent execution units and two register ?es bpu featuring static branch prediction a 32-bit iu fully ieee 754-compliant fpu for both single- and double-precision operations lsu for data transfer between data cache and gprs and fprs sru that executes condition register (cr) and special-purpose register (spr) instructions thirty-two gprs for integer operands thirty-two fprs for single- or double-precision operands high instruction and data throughput zero-cycle branch capability (branch folding) programmable static branch prediction on unresolved conditional branches instruction fetch unit capable of fetching two instructions per clock from the instruction cache a six-entry instruction queue that provides look-ahead capability independent pipelines with feed-forwarding that reduces data dependencies in hardware 8-kbyte data cache?wo-way set-associative, physically addressed; lru replacement algorithm 8-kbyte instruction cache?wo-way set-associative, physically addressed; lru replacement algorithm cache write-back or write-through operation programmable on a per page or per block basis bpu that performs cr look-ahead operations address translation facilities for 4-kbyte page size, variable block size, and 256-mbyte segment size a 64-entry, two-way set-associative itlb a 64-entry, two-way set-associative dtlb four-entry data and instruction bat arrays providing 128-kbyte to 256-mbyte blocks software table search operations and updates supported through fast trap mechanism 52-bit virtual address; 32-bit physical address facilities for enhanced system performance a 32- or 64-bit split-transaction external data bus with burst transfers support for one-level address pipelining and out-of-order bus transactions bus extensions for direct-store interface operations integrated power management low-power 3.3-volt design internal processor/bus clock multiplier that provides 1/1, 2/1, 3/1, and 4/1 ratios three power saving modes: doze, nap, and sleep automatic dynamic power reduction when internal functional units are idle in-system testability and debugging features through jtag boundary-scan capability 4 powerpc 603 risc microprocessor technical summary 1.2 block diagram figure 1 provides a block diagram of the 603 that illustrates how the execution units?u, fpu, bpu, lsu, and sru?perate independently and in parallel. the 603 provides address translation and protection facilities, including an itlb, dtlb, and instruction and data bat arrays. instruction fetching and issuing is handled in the instruction unit. translation of addresses for cache or external memory accesses are handled by the mmus. both units are discussed in more detail in sections 1.3, ?nstruction unit,?and 1.5.1, ?emory management units (mmus). 1.3 instruction unit as shown in figure 1, the 603 instruction unit, which contains a fetch unit, instruction queue, dispatch unit, and bpu, provides centralized control of instruction ?w to the execution units. the instruction unit determines the address of the next instruction to be fetched based on information from the sequential fetcher and from the bpu. the instruction unit fetches the instructions from the instruction cache into the instruction queue. the bpu extracts branch instructions from the fetcher and uses static branch prediction on unresolved conditional branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while a conditional branch is evaluated. the bpu folds out branch instructions for unconditional branches or conditional branches unaffected by instructions in progress in the execution pipeline. instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. if any of these instructions are to be executed in the bpu, they are decoded but not issued. instructions to be executed by the fpu, iu, lsu, and sru are issued and allowed to complete up to the register write-back stage. write-back is allowed when a correctly predicted branch is resolved, and instruction execution continues without interruption along the predicted path. if branch prediction is incorrect, the instruction unit ?shes all predicted path instructions, and instructions are issued from the correct path. powerpc 603 risc microprocessor technical summary 5 figure 1. powerpc 603 microprocessor block diagram branch processing unit 32-/64-bit data bus 32-bit address bus instruction unit integer unit floating- point unit fpr file fp rename registers 8-kbyte d cache tags sequential fetcher ctr cr lr + * / fpscr system register unit + * / processor bus interface d mmu srs dtlb dbat array touch load buffer copyback buffer 64 bit 32 bit dispatch unit 64 bit 64 bit power dissipation control completion unit time base counter/ decrementer clock multiplier jtag/cop interface xer i mmu srs itlb ibat array 8-kbyte i cache tags 64 bit 64 bit 64 bit 64 bit 64 bit gpr file load/store unit + 64-bit gp rename registers instruction queue 6 powerpc 603 risc microprocessor technical summary 1.3.1 instruction queue and dispatch unit the instruction queue (iq), shown in figure 1, holds as many as six instructions and loads up to two instructions from the instruction unit during a single cycle. the instruction fetch unit continuously loads as many instructions as space in the iq allows. instructions are dispatched to their respective execution units from the dispatch unit at a maximum rate of two instructions per cycle. dispatching is facilitated to the iu, fpu, lsu, and sru by the provision of a reservation station at each unit. the dispatch unit performs source and destination register dependency checking, determines dispatch serializations, and inhibits subsequent instruction dispatching as required. for a more detailed overview of instruction dispatch, see section 3.7, ?nstruction timing. 1.3.2 branch processing unit (bpu) the bpu receives branch instructions from the fetch unit and performs cr look-ahead operations on conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many cases. the bpu uses a bit in the instruction encoding to predict the direction of the conditional branch. therefore, when an unresolved conditional branch instruction is encountered, the 603 fetches instructions from the predicted target stream until the conditional branch is resolved. the bpu contains an adder to compute branch target addresses and three user-control registers?he link register (lr), the count register (ctr), and the cr. the bpu calculates the return pointer for subroutine calls and saves it into the lr for certain types of branch instructions. the lr also contains the branch target address for the branch conditional to link register ( bclr x ) instruction. the ctr contains the branch target address for the branch conditional to count register ( bcctr x ) instruction. the contents of the lr and ctr can be copied to or from any gpr. because the bpu uses dedicated registers rather than gprs or fprs, execution of branch instructions is largely independent from execution of integer and ?ating-point instructions. 1.4 independent execution units the powerpc architecture s support for independent execution units allows implementation of processors with out-of-order instruction execution. for example, because branch instructions do not depend on gprs or fprs, branches can often be resolved early, eliminating stalls caused by taken branches. in addition to the bpu, the 603 provides four other execution units and a completion unit, which are described in the following sections. 1.4.1 integer unit (iu) the iu executes all integer instructions. the iu executes one integer instruction at a time, performing computations with its arithmetic logic unit (alu), multiplier, divider, and integer exception register (xer). most integer instructions are single-cycle instructions. thirty-two general-purpose registers are provided to support integer operations. stalls due to contention for gprs are minimized by the automatic allocation of rename registers. the 603 writes the contents of the rename registers to the appropriate gpr when integer instructions are retired by the completion unit. 1.4.2 floating-point unit (fpu) the fpu contains a single-precision multiply-add array and the ?ating-point status and control register (fpscr). the multiply-add array allows the 603 to ef?iently implement multiply and multiply-add operations. the fpu is pipelined so that single-precision instructions and double-precision instructions can be issued back-to-back. thirty-two ?ating-point registers are provided to support ?ating-point operations. stalls due to contention for fprs are minimized by the automatic allocation of rename registers. the 603 powerpc 603 risc microprocessor technical summary 7 writes the contents of the rename registers to the appropriate fpr when ?ating-point instructions are retired by the completion unit. the 603 supports all ieee 754 ?ating-point data types (normalized, denormalized, nan, zero, and in?ity) in hardware, eliminating the latency incurred by software exception routines. (the term, ?xception is also referred to as ?nterrupt in the architecture speci?ation.) 1.4.3 load/store unit (lsu) the lsu executes all load and store instructions and provides the data transfer interface between the gprs, fprs, and the cache/memory subsystem. the lsu calculates effective addresses, performs data alignment, and provides sequencing for load/store string and multiple instructions. load and store instructions are issued and translated in program order; however, the actual memory accesses can occur out of order. synchronizing instructions are provided to enforce strict ordering. cacheable loads, when free of data dependencies, execute in a speculative manner with a maximum throughput of one per cycle and a two-cycle total latency. data returned from the cache is held in a rename register until the completion logic commits the value to a gpr or fpr. stores cannot be executed speculatively and are held in the store queue until the completion logic signals that the store operation is to be completed to memory. the time required to perform the actual load or store operation varies depending on whether the operation involves the cache, system memory, or an i/o device. 1.4.4 system register unit (sru) the sru executes various system-level instructions, including condition register logical operations and move to/from special-purpose register instructions. in order to maintain system state, most instructions executed by the sru are completion-serialized; that is, the instruction is held for execution in the sru until all prior instructions issued have completed. results from completion-serialized instructions executed by the sru are not available or forwarded for subsequent instructions until the instruction completes. 1.4.5 completion unit the completion unit tracks instructions from dispatch through execution, and then retires, or ?ompletes them in program order. completing an instruction commits the 603 to any architectural register changes caused by that instruction. in-order completion ensures the correct architectural state when the 603 must recover from a mispredicted branch or any exception. instruction state and other information required for completion is kept in a ?st-in-?st-out (fifo) queue of ?e completion buffers. a single completion buffer is allocated for each instruction once it enters the dispatch unit. an available completion buffer is a required resource for instruction dispatch; if no completion buffers are available, instruction dispatch stalls. a maximum of two instructions per cycle are completed in order from the queue. 1.5 memory subsystem support the 603 provides support for cache and memory management through dual instruction and data memory management units. the 603 also provides dual 8-kbyte instruction and data caches, and an ef?ient processor bus interface to facilitate access to main memory and other bus subsystems. the memory subsystem support functions are described in the following subsections. 1.5.1 memory management units (mmus) the 603 s mmus support up to 4 petabytes (2 52 ) of virtual memory and 4 gigabytes (2 32 ) of physical memory (referred to as real memory in the architecture speci?ation) for instruction and data. the mmus also control access privileges for these spaces on block and page granularities. referenced and changed 8 powerpc 603 risc microprocessor technical summary status is maintained by the processor for each page to assist implementation of a demand-paged virtual memory system. the lsu calculates effective addresses for data loads and stores, performs data alignment to and from cache memory, and provides the sequencing for load and store string and multiple word instructions. the instruction unit calculates the effective addresses for instruction fetching. after an address is generated, the higher-order bits of the effective address are translated by the appropriate mmu into physical address bits. simultaneously, the lower-order address bits (that are untranslated and therefore, considered both logical and physical), are directed to the on-chip caches where they form the index into the two-way set-associative tag array. after translating the address, the mmu passes the higher- order bits of the physical address to the cache, and the cache lookup completes. for cache-inhibited accesses or accesses that miss in the cache, the untranslated lower-order address bits are concatenated with the translated higher-order address bits; the resulting 32-bit physical address is then used by the memory unit and the system interface, which accesses external memory. the mmu also directs the address translation and enforces the protection hierarchy programmed by the operating system in relation to the supervisor/user privilege level of the access and in relation to whether the access is a load or store. for instruction accesses, the mmu performs an address lookup in both the 64 entries of the itlb, and in the ibat array. if an effective address hits in both the itlb and the ibat array, the ibat array translation takes priority. data accesses cause a lookup in the dtlb and dbat array for the physical address translation. in most cases, the physical address translation resides in one of the tlbs and the physical address bits are readily available to the on-chip cache. when the physical address translation misses in the tlbs, the 603 provides hardware assistance for software to perform a search of the translation tables in memory. the hardware assist consists of the following features: automatic storage of the missed effective address in the imiss and dmiss registers automatic generation of the primary and secondary hashed real address of the page table entry group (pteg), which are readable from the hash1 and hash2 register locations the hash data is generated from the contents of the imiss or dmiss register. which register is selected depends on which miss (instruction or data) was last acknowledged. automatic generation of the ?st word of the page table entry (pte) for which the tables are being searched a real page address (rpa) register that matches the format of the lower word of the pte two tlb access instructions ( tlbli and tlbld ) that are used to load an address translation into the instruction or data tlbs shadow registers for gprs 0? that allow miss code to execute without corrupting the state of any of the existing gprs these shadow registers are only used for servicing a tlb miss. see section 3.6.2, ?owerpc 603 microprocessor memory management,?for more information about memory management for the 603. 1.5.2 cache units the 603 provides independent 8-kbyte, two-way set-associative instruction and data caches. the cache line size is 32 bytes in length. the caches are designed to adhere to a write-back policy, but the 603 allows control of cacheability, write policy, and memory coherency at the page and block levels. the caches use a least recently used (lru) replacement policy. powerpc 603 risc microprocessor technical summary 9 as shown in figure 1, the caches provide a 64-bit interface to the instruction fetch unit and load/store unit. the surrounding logic selects, organizes, and forwards the requested information to the requesting unit. write operations to the cache can be performed on a byte basis, and a complete read-modify-write operation to the cache can occur in each cycle. the load/store and instruction fetch units provide the caches with the address of the data or instruction to be fetched. in the case of a cache hit, the cache returns two words to the requesting unit. since the 603 data cache tags are single ported, simultaneous load or store and snoop accesses cause resource contention. snoop accesses have the highest priority and are given ?st access to the tags, unless the snoop access coincides with a tag write, in which case the snoop is retried and must re-arbitrate for access to the cache. loads or stores that are deferred due to snoop accesses are executed on the clock cycle following the snoop. 1.6 processor bus interface because the caches on the 603 are on-chip, write-back caches, the predominant type of transaction for most applications is burst-read memory operations, followed by burst-write memory operations, single-beat (noncacheable or write-through) memory read and write operations, and direct-store interface operations. additionally, there can be address-only operations, variants of the burst and single-beat operations, (for example, global memory operations that are snooped and atomic memory operations), and address retry activity (for example, when a snooped read access hits a modi?d line in the cache). memory accesses can occur in single-beat (1? bytes) and four-beat burst (32 bytes) data transfers when the bus is con?ured as 64 bits, and in single-beat (1? bytes), two-beat (8 bytes), and eight-beat (32 bytes) data transfers when the bus is con?ured as 32 bits. the address and data buses operate independently to support pipelining and split transactions during memory accesses. the 603 can pipeline its own transactions to a depth of one level. access to the system interface is granted through an external arbitration mechanism that allows devices to compete for bus mastership. this arbitration mechanism is ?xible, allowing the 603 to be integrated into systems that implement various fairness and bus parking procedures to avoid arbitration overhead. typically, memory accesses are weakly ordered?equences of operations, including load/store string and multiple instructions, do not necessarily complete in the order they begin?aximizing the ef?iency of the bus without sacri?ing coherency of the data. the 603 allows read operations to precede store operations (except when a dependency exists). because the processor can dynamically optimize run-time ordering of load/store traf?, overall performance is improved. 1.7 system support functions the 603 implements several support functions that include power management, time base/decrementer registers for system timing tasks, an ieee 1149.1(jtag)/common on-chip processor (cop) test interface, and a phase-locked loop (pll) clock multiplier. these system support functions are described in the following subsections. 1.7.1 power management the 603 provides four power modes selectable by setting the appropriate control bits in the machine state register (msr) and hardware implementation register 0 (hid0) registers. the four power modes are as follows: 10 powerpc 603 risc microprocessor technical summary full-power?his is the default power state of the 603. the 603 is fully powered and the internal functional units are operating at the full processor clock speed. if the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution, or external hardware. doze?ll the functional units of the 603 are disabled except for the time base/decrementer registers and the bus snooping logic. when the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine check brings the 603 into the full-power state. the 603 in doze mode maintains the pll in a fully powered state and locked to the system external clock input (sysclk) so a transition to the full- power state takes only a few processor clock cycles. nap?he nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the pll in a powered state. the 603 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or a machine check input (mcp ). a return to full-power state from a nap state takes only a few processor clock cycles. sleep?leep mode reduces power consumption to a minimum by disabling all internal functional units, after which external system logic may disable the pll and sysclk. returning the 603 to the full-power state requires the enabling of the pll and sysclk, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine check input (mcp ) signal after the time required to relock the pll. 1.7.2 time base/decrementer the time base is a 64-bit register (accessed as two 32-bit registers) that is incremented once every four bus clock cycles; external control of the time base is provided through the time base enable (tben) signal. the decrementer is a 32-bit register that generates a decrementer exception after a programmable delay. the contents of the decrementer register are decremented once every four bus clock cycles, and the decrementer exception is generated as the count passes through zero. 1.7.3 ieee 1149.1 (jtag)/cop test interface the 603 provides ieee 1149.1 and cop functions for facilitating board testing and chip debug. the ieee 1149.1 test interface provides a means for boundary-scan testing the 603 and the board to which it is attached. the cop function shares the ieee 1149.1 test port, provides a means for executing test routines, and facilitates chip and software debugging. 1.7.4 clock multiplier the internal clocking of the 603 is generated from and synchronized to the external clock signal, sysclk, by means of a voltage-controlled oscillator-based pll. the pll provides programmable internal processor clock rates of 1x, 2x, 3x, and 4x multiples of the externally supplied clock frequency. the bus clock is the same frequency and is synchronous with sysclk. part 2 levels of the powerpc architecture the powerpc architecture consists of the following layers, and adherence to the powerpc architecture can be measured in terms of which of the following levels of the architecture is implemented: powerpc user instruction set architecture (uisa)?e?es the base user-level instruction set, user- level registers, data types, ?ating-point exception model, memory models for a uniprocessor environment, and programming model for a uniprocessor environment. powerpc 603 risc microprocessor technical summary 11 powerpc virtual environment architecture (vea)?escribes the memory model for a multiprocessor environment, de?es cache control instructions, and describes other aspects of virtual environments. implementations that conform to the vea also adhere to the uisa, but may not necessarily adhere to the oea. powerpc operating environment architecture (oea)?e?es the memory management model, supervisor-level registers, synchronization requirements, and the exception model. implementations that conform to the oea also adhere to the uisa and the vea. the powerpc architecture allows a wide range of designs for such features as cache and system interface implementations. part 3 powerpc 603 microprocessor: implementation the powerpc architecture is derived from the ibm power architecture (performance optimized with enhanced risc architecture). the powerpc architecture shares the bene?s of the power architecture optimized for single-chip implementations. the powerpc architecture design facilitates parallel instruction execution and is scalable to take advantage of future technological gains. this section describes the powerpc architecture in general, and speci? details about the implementation of the 603 as a low-power, 32-bit member of the powerpc processor family. features?ection 3.1, ?eatures,?describes general features that the 603 shares with the powerpc microprocessor family. registers and programming model?ection 3.2, ?owerpc registers and programming model,? describes the registers for the operating environment architecture common among powerpc processors and describes the programming model. it also describes the additional registers that are unique to the 603. instruction set and addressing modes?ection 3.3, ?nstruction set and addressing modes,? describes the powerpc instruction set and addressing modes for the powerpc operating environment architecture, and de?es and describes the powerpc instructions implemented in the 603. cache implementation?ection 3.4, ?ache implementation,?describes the cache model that is de?ed generally for powerpc processors by the virtual environment architecture. it also provides speci? details about the 603 cache implementation. exception model?ection 3.5, ?xception model,?describes the exception model of the powerpc operating environment architecture and the differences in the 603 exception model. memory management?ection 3.6, ?emory management,?describes generally the conventions for memory management among the powerpc processors. this section also describes the 603 s implementation of the 32-bit powerpc memory management speci?ation. instruction timing?ection 3.7, ?nstruction timing,?provides a general description of the instruction timing provided by the superscalar, parallel execution supported by the powerpc architecture and the 603. system interface?ection 3.8, ?ystem interface,?describes the signals implemented on the 603. 3.1 features the 603 is a high-performance, superscalar powerpc microprocessor. the powerpc architecture allows optimizing compilers to schedule instructions to maximize performance through ef?ient use of the powerpc instruction set and register model. the multiple, independent execution units allow compilers to optimize instruction throughput. compilers that take advantage of the ?xibility of the powerpc architecture can additionally optimize system performance of the powerpc processors. 12 powerpc 603 risc microprocessor technical summary speci? features of the 603 are listed in section 1.1, ?owerpc 603 microprocessor features. 3.2 powerpc registers and programming model the powerpc architecture de?es register-to-register operations for most computational instructions. source operands for these instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode. the three-register instruction format allows speci?ation of a target register distinct from the two source operands. load and store instructions transfer data between registers and memory. powerpc processors have two levels of privilege?upervisor mode of operation (typically used by the operating system) and user mode of operation (used by the application software). the programming models incorporate 32 gprs, 32 fprs, special-purpose registers (sprs), and several miscellaneous registers. each powerpc microprocessor also has its own unique set of hardware implementation (hid) registers. having access to privileged instructions, registers, and other resources allows the operating system to control the application environment (providing virtual memory and protecting operating-system and critical machine resources). instructions that control the state of the processor, the address translation mechanism, and supervisor registers can be executed only when the processor is operating in supervisor mode. the following sections summarize the powerpc registers that are implemented in the 603. 3.2.1 general-purpose registers (gprs) the powerpc architecture de?es 32 user-level, general-purpose registers (gprs). these registers are either 32 bits wide in 32-bit powerpc microprocessors and 64 bits wide in 64-bit powerpc microprocessors. the gprs serve as the data source or destination for all integer instructions. 3.2.2 floating-point registers (fprs) the powerpc architecture also de?es 32 user-level, 64-bit ?ating-point registers (fprs). the fprs serve as the data source or destination for ?ating-point instructions. these registers can contain data objects of either single- or double-precision ?ating-point formats. 3.2.3 condition register (cr) the cr is a 32-bit user-level register that consists of eight four-bit ?lds that re?ct the results of certain operations, such as move, integer and ?ating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. 3.2.4 floating-point status and control register (fpscr) the ?ating-point status and control register (fpscr) is a user-level register that contains all exception signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance with the ieee 754 standard. 3.2.5 machine state register (msr) the machine state register (msr) is a supervisor-level register that de?es the state of the processor. the contents of this register are saved when an exception is taken and restored when the exception handling completes. the 603 implements the msr as a 32-bit register; 64-bit powerpc processors implement a 64- bit msr. powerpc 603 risc microprocessor technical summary 13 3.2.6 segment registers (srs) for memory management, 32-bit powerpc microprocessors implement sixteen 32-bit segment registers (srs). to speed access, the 603 implements the segment registers as two arrays; a main array (for data memory accesses) and a shadow array (for instruction memory accesses). loading a segment entry with the move to segment register ( mtsr ) instruction loads both arrays. 3.2.7 special-purpose registers (sprs) the powerpc operating environment architecture de?es numerous special-purpose registers that serve a variety of functions, such as providing controls, indicating status, con?uring the processor, and performing special operations. during normal execution, a program can access the registers, shown in figure 2, depending on the program s access privilege (supervisor or user, determined by the privilege-level (pr) bit in the msr). note that registers such as the gprs and fprs are accessed through operands that are part of the instructions. access to registers can be explicit (that is, through the use of speci? instructions for that purpose such as move to special-purpose register ( mtspr ) and move from special-purpose register ( mfspr ) instructions) or implicit, as the part of the execution of an instruction. some registers are accessed both explicitly and implicitly in the 603, all sprs are 32 bits wide. 3.2.7.1 user-level sprs the following 603 sprs are accessible by user-level software: link register (lr)?he link register can be used to provide the branch target address and to hold the return address after branch and link instructions. the lr is 32 bits wide in 32-bit implementations. count register (ctr)?he ctr is decremented and tested automatically as a result of branch-and- count instructions. the ctr is 32 bits wide in 32-bit implementations. integer exception register (xer)?he 32-bit xer contains the summary over?w bit, integer carry bit, over?w bit, and a ?ld specifying the number of bytes to be transferred by a load string word indexed ( lswx ) or store string word indexed ( stswx ) instruction. 3.2.7.2 supervisor-level sprs the 603 also contains sprs that can be accessed only by supervisor-level software. these registers consist of the following: the 32-bit dsisr de?es the cause of data access and alignment exceptions. the data address register (dar) is a 32-bit register that holds the address of an access after an alignment or dsi exception. decrementer register (dec) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay. the 32-bit sdr1 speci?s the page table format used in virtual-to-physical address translation for pages. (note that physical address is referred to as real address in the architecture speci?ation.) the machine status save/restore register 0 (srr0) is a 32-bit register that is used by the 603 for saving the address of the instruction that caused the exception, and the address to return to when a return from interrupt ( r ) instruction is executed. the machine status save/restore register 1 (srr1) is a 32-bit register used to save machine status on exceptions and to restore machine status when an r instruction is executed. the 32-bit sprg0?prg3 registers are provided for operating system use. 14 powerpc 603 risc microprocessor technical summary the external access register (ear) is a 32-bit register that controls access to the external control facility through the external control in word indexed ( eciwx ) and external control out word indexed ( ecowx ) instructions. the time base register (tb) is a 64-bit register that maintains the time of day and operates interval timers. the tb consists of two 32-bit ?lds?ime base upper (tbu) and time base lower (tbl). the processor version register (pvr) is a 32-bit, read-only register that identi?s the version (model) and revision level of the powerpc processor. block address translation (bat) arrays?he powerpc architecture de?es 16 bat registers, divided into four pairs of data bats (dbats) and four pairs of instruction bats (ibats). see figure 2 for a list of the spr numbers for the bat arrays. the following supervisor-level sprs are implementation-speci? to the 603: the dmiss and imiss registers are read-only registers that are loaded automatically upon an instruction or data tlb miss. the hash1 and hash2 registers contain the physical addresses of the primary and secondary page table entry groups (ptegs). the icmp and dcmp registers contain a duplicate of the ?st word in the page table entry (pte) for which the table search is looking. the required physical address (rpa) register is loaded by the processor with the second word of the correct pte during a page table search. the hardware implementation (hid0) register provides means for enabling the 603 s checkstops and features. the instruction address breakpoint register (iabr) is loaded with an instruction address that is compared to instruction addresses in the dispatch queue. when an address match occurs, an instruction address breakpoint exception is generated. figure 2 shows all the 603 registers available at the user and supervisor level. the numbers to the right of the sprs indicate the number that is used in the syntax of the instruction operands to access the register. powerpc 603 risc microprocessor technical summary 15 figure 2. powerpc 603 microprocessor programming model?egisters dsisr spr 18 dsisr data address register spr 19 dar spr 26 srr0 spr 27 srr1 sprgs spr 272 sprg0 spr 273 sprg1 spr 274 sprg2 spr 275 sprg3 exception handling registers save and restore instruction bat registers spr 528 ibat0u spr 529 ibat0l spr 530 ibat1u spr 531 ibat1l spr 532 ibat2u spr 533 ibat2l spr 534 ibat3u spr 535 ibat3l data bat registers spr 536 dbat0u spr 537 dbat0l spr 538 dbat1u spr 539 dbat1l spr 540 dbat2u spr 541 dbat2l spr 542 dbat3u spr 543 dbat3l memory management registers software table search registers 1 spr 976 dmiss spr 977 dcmp spr 978 hash1 spr 979 hash2 spr 980 imiss spr 981 icmp spr 982 rpa machine state register msr processor version register spr 287 pvr configuration registers hardware implementation register 1 spr1 008 hid0 tbr 268 tbl tbr 269 tbu spr 1 user model floating-point status and control register cr fpscr condition register gpr0 gpr1 gpr31 general-purpose registers floating-point registers xer xer spr 8 link register lr time base facility (for reading) supervisor model spr 22 decrementer dec time base facility (for writing) spr 284 tbl spr 285 tbu spr 282 external address register (optional) ear sdr1 spr 25 sdr1 spr 9 count register ctr miscellaneous registers spr 1010 iabr instruction address breakpoint register 1 segment registers sr0 sr1 sr15 fpr0 fpr1 fpr31 1 these registers are 603?peci? registers. they may not be supported by other powerpc processors. 16 powerpc 603 risc microprocessor technical summary 3.3 instruction set and addressing modes the following subsections describe the powerpc instruction set and addressing modes in general. 3.3.1 powerpc instruction set and addressing modes all powerpc instructions are encoded as single-word (32-bit) opcodes. instruction formats are consistent among all instruction types, permitting ef?ient decoding to occur in parallel with operand accesses. this ?ed instruction length and consistent format greatly simpli?s instruction pipelining. 3.3.1.1 powerpc instruction set the powerpc instructions are divided into the following categories: integer instructions?hese include computational and logical instructions. integer arithmetic instructions integer compare instructions integer logical instructions integer rotate and shift instructions floating-point instructions?hese include ?ating-point computational instructions, as well as instructions that affect the fpscr. floating-point arithmetic instructions floating-point multiply/add instructions floating-point rounding and conversion instructions floating-point compare instructions floating-point status and control instructions load/store instructions?hese include integer and ?ating-point load and store instructions. integer load and store instructions integer load and store multiple instructions floating-point load and store primitives used to construct atomic memory operations ( lwarx and stwcx. instructions) flow control instructions?hese include branching instructions, condition register logical instructions, trap instructions, and other instructions that affect the instruction ?w. branch and trap instructions condition register logical instructions processor control instructions?hese instructions are used for synchronizing memory accesses and management of caches, tlbs, and the segment registers. move to/from spr instructions move to/from msr synchronize instruction synchronize memory control instructions?hese instructions provide control of caches, tlbs, and segment registers. supervisor-level cache management instructions user-level cache instructions segment register manipulation instructions translation lookaside buffer management instructions powerpc 603 risc microprocessor technical summary 17 note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions. integer instructions operate on byte, half-word, and word operands. floating-point instructions operate on single-precision (one word) and double-precision (one double word) ?ating-point operands. the powerpc architecture uses instructions that are four bytes long and word-aligned. it provides for byte, half-word, and word operand loads and stores between memory and a set of 32 gprs. it also provides for word and double- word operand loads and stores between memory and a set of 32 ?ating-point registers (fprs). computational instructions do not modify memory. to use a memory operand in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modi?d, and then written back to the target location with distinct instructions. powerpc processors follow the program ?w when they are in the normal execution state. however, the ?w of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event. either kind of exception may cause one of several components of the system software to be invoked. 3.3.1.2 calculating effective addresses the effective address (ea) is the 32-bit address computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction. the powerpc architecture supports two simple memory addressing modes: ea = ( r a|0) + offset (including offset = 0) (register indirect with immediate index) ea = ( r a|0) + r b (register indirect with index) these simple addressing modes allow ef?ient address generation for memory accesses. calculation of the effective address for aligned transfers occurs in a single clock cycle. for a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the memory operand is considered to wrap around from the maximum effective address to effective address 0. effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. a carry from bit 0 is ignored in 32-bit implementations. 3.3.2 powerpc 603 microprocessor instruction set the 603 instruction set is de?ed as follows: the 603 provides hardware support for all 32-bit powerpc instructions. the 603 provides two implementation-speci? instructions used for software table search operations following tlb misses: load data tlb entry ( tlbld ) load instruction tlb entry ( tlbli ) the 603 implements the following instructions which are de?ed as optional by the powerpc architecture: external control in word indexed ( eciwx ) external control out word indexed ( ecowx ) floating select ( fsel ) floating reciprocal estimate single-precision ( fres ) floating reciprocal square root estimate ( frsqrte ) store floating-point as integer word ( st?x ) 18 powerpc 603 risc microprocessor technical summary 3.4 cache implementation the following subsections describe the powerpc architecture s treatment of cache in general, and the 603- speci? implementation, respectively. 3.4.1 powerpc cache characteristics the powerpc architecture does not de?e hardware aspects of cache implementations. for example, some powerpc processors, including the 603, have separate instruction and data caches (harvard architecture), while others, such as the powerpc 601 microprocessor, implement a uni?d cache. powerpc microprocessors control the following memory access modes on a page or block basis: write-back/write-through mode cache-inhibited mode memory coherency note that in the 603, a cache line is de?ed as eight words. the vea de?es cache management instructions that provide a means by which the application programmer can affect the cache contents. 3.4.2 powerpc 603 microprocessor cache implementation the 603 has two 8-kbyte, two-way set-associative (instruction and data) caches. the caches are physically addressed, and the data cache can operate in either write-back or write-through mode as speci?d by the powerpc architecture. the data cache is con?ured as 128 sets of 2 lines each. each line consists of 32 bytes, two state bits, and an address tag. the two state bits implement the three-state mei (modi?d/exclusive/invalid) protocol. each line contains eight 32-bit words. note that the powerpc architecture de?es the term block as the cacheable unit. for the 603, the block size is equivalent to a cache line. a block diagram of the data cache organization is shown in figure 3. the instruction cache also consists of 128 sets of 2 lines, and each line consists of 32 bytes, an address tag, and a valid bit. the instruction cache may not be written to except through a line ?l operation. the instruction cache is not snooped, and cache coherency must be maintained by software. a fast hardware invalidation capability is provided to support cache maintenance. the organization of the instruction cache is very similar to the data cache shown in figure 3. each cache line contains eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits a27?31 of the effective addresses are zero); thus, a cache line never crosses a page boundary. misaligned accesses across a page boundary can incur a performance penalty. the 603 s cache lines are loaded in four beats of 64 bits each. the burst load is performed as ?ritical double word ?st.?the cache that is being loaded is blocked to internal accesses until the load completes. the critical double word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to load delays. to ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the 603 implements the mei protocol. these three states, modi?d, exclusive, and invalid, indicate the state of the cache block as follows: modi?d?he cache line is modi?d with respect to system memory; that is, data for this address is valid only in the cache and not in system memory. exclusive?his cache line holds valid data that is identical to the data at this address in system memory. no other cache has this data. invalid?his cache line does not hold valid data. powerpc 603 risc microprocessor technical summary 19 cache coherency is enforced by on-chip bus snooping logic. since the 603 s data cache tags are single ported, a simultaneous load or store and snoop access represent a resource contention. the snoop access is given ?st access to the tags. the load or store then occurs on the clock following the snoop. figure 3. data cache organization 3.5 exception model the following subsections describe the powerpc exception model and the 603 implementation, respectively. 3.5.1 powerpc exception model the powerpc exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions arising in the execution of instructions, and differ from the arithmetic exceptions de?ed by the ieee for ?ating-point operations. when exceptions occur, information about the state of the processor is saved to certain registers and the processor begins execution at an address (exception vector) predetermined for each exception. processing of exceptions occurs in supervisor mode. although multiple exception conditions can map to a single exception vector, a more speci? condition may be determined by examining a register associated with the exception?or example, the dsisr and the fpscr. additionally, some exception conditions can be explicitly enabled or disabled by software. the powerpc architecture requires that exceptions be handled in program order; therefore, although a particular implementation may recognize exception conditions out of order, they are presented strictly in order. when an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute state, are required to complete before the exception is taken. any exceptions caused by those instructions are handled ?st. likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the instruction currently in the completion stage successfully completes execution or generates an exception, and the completed store queue is emptied. unless a catastrophic condition causes a system reset or machine check exception, only one exception is handled at a time. if, for example, a single instruction encounters multiple exception conditions, those conditions are encountered sequentially. after the exception handler handles an exception, the instruction execution continues until the next exception condition is encountered. however, in many cases there is no attempt to re-execute the instruction. this method of recognizing and handling exception conditions sequentially guarantees that exceptions are recoverable. exception handlers should save the information stored in srr0 and srr1 early to prevent the program state from being lost due to a system reset and machine check exception or to an instruction-caused exception in the exception handler, and before enabling external interrupts. address tag 1 block 1 128 sets address tag 0 block 0 8 words/block state state words 0? words 0? 20 powerpc 603 risc microprocessor technical summary the powerpc architecture supports four types of exceptions: synchronous, precise?hese are caused by instructions. all instruction-caused exceptions are handled precisely; that is, the machine state at the time the exception occurs is known and can be completely restored. this means that (excluding the trap and system call exceptions) the address of the faulting instruction is provided to the exception handler and that neither the faulting instruction nor subsequent instructions in the code stream will complete execution before the exception is taken. once the exception is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception handler). when an exception is taken due to a trap or system call instruction, execution resumes at an address provided by the handler. synchronous, imprecise?he powerpc architecture de?es two imprecise ?ating-point exception modes, recoverable and nonrecoverable. even though the 603 provides a means to enable the imprecise modes, it implements these modes identically to the precise mode (that is, all enabled ?ating-point enabled exceptions are always precise on the 603). asynchronous, maskable?he external, smi, and decrementer interrupts are maskable asynchronous exceptions. when these exceptions occur, their handling is postponed until the next instruction, and any exceptions associated with that instruction, completes execution. if there are no instructions in the execution units, the exception is taken immediately upon determination of the correct restart address (for loading srr0). asynchronous, nonmaskable?here are two nonmaskable asynchronous exceptions: system reset and the machine check exception. these exceptions may not be recoverable, or may provide a limited degree of recoverability. all exceptions report recoverability through the msr[ri] bit. 3.5.2 powerpc 603 microprocessor exception model as speci?d by the powerpc architecture, all 603 exceptions can be described as either precise or imprecise and either synchronous or asynchronous. asynchronous exceptions (some of which are maskable) are caused by events external to the processor s execution; synchronous exceptions, which are all handled precisely by the 603, are caused by instructions. the 603 exception classes are shown in table 1. although exceptions have other characteristics as well, such as whether they are maskable or nonmaskable, the distinctions shown in table 1 de?e categories of exceptions that the 603 handles uniquely. note that table 1 includes no synchronous imprecise instructions. while the powerpc architecture supports imprecise handling of ?ating-point exceptions, the 603 implements these exception modes as precise exceptions. the 603 s exceptions, and conditions that cause them, are listed in table 2. exceptions that are speci? to the 603 are indicated. table 1. powerpc 603 microprocessor exception classifications synchronous/asynchronous precise/imprecise exception type asynchronous, nonmaskable imprecise machine check system reset asynchronous, maskable precise external interrupt decrementer system management interrupt synchronous precise instruction-caused exceptions powerpc 603 risc microprocessor technical summary 21 table 2. exceptions and conditions exception type vector offset (hex) causing conditions reserved 00000 system reset 00100 a system reset is caused by the assertion of either sreset or hreset . machine check 00200 a machine check is caused by the assertion of the tea signal during a data bus transaction, assertion of mcp , or an address or data parity error. dsi 00300 the cause of a dsi exception can be determined by the bit settings in the dsisr, listed as follows: 1 set if the translation of an attempted access is not found in the primary hash table entry group (hteg), or in the rehashed secondary hteg, or in the range of a dbat register; otherwise cleared. 4 set if a memory access is not permitted by the page or dbat protection mechanism; otherwise cleared. 5 set if the access was to an i/o segment (sr[t] =1) by an eciwx , ecowx, lwarx , or stwcx . instruction; otherwise cleared. 6 set for a store operation and cleared for a load operation. 11 set if eciwx or ecowx is used and ear[e] is cleared. isi 00400 an isi exception is caused when an instruction fetch cannot be performed for any of the following reasons: the effective (logical) address cannot be translated. that is, there is a page fault for this portion of the translation, so an isi exception must be taken to load the pte (and possibly the page) into memory. the fetch access is to a direct-store segment. the fetch access violates memory protection. if the key bits (ks and kp) in the segment register and the pp bits in the pte are set to prohibit read access, instructions cannot be fetched from this location. external interrupt 00500 an external interrupt is caused when msr[ee] = 1 and the int signal is asserted. alignment 00600 an alignment exception is caused when the 603 cannot perform a memory access for any of several reasons, such as when the operand of a ?ating-point load or store operation is in an i/o segment (sr[t] = 1). 22 powerpc 603 risc microprocessor technical summary program 00700 a program exception is caused by one of the following exception conditions, which correspond to bit settings in srr1 and arise during execution of an instruction: floating-point enabled exception? ?ating-point enabled exception condition is generated when the following condition is met: (msr[fe0] | msr[fe1]) & fpscr[fex] is 1. fpscr[fex] is set by the execution of a ?ating-point instruction that causes an enabled exception or by the execution of one of the ?ove to fpscr instructions that results in both an exception condition bit and its corresponding enable bit being set in the fpscr. illegal instruction?n illegal instruction program exception is generated when execution of an instruction is attempted with an illegal opcode or illegal combination of opcode and extended opcode ?lds (including powerpc instructions not implemented in the 603), or when execution of an optional instruction not provided in the 603 is attempted (these do not include those optional instructions that are treated as no-ops). privileged instruction? privileged instruction type program exception is generated when the execution of a privileged instruction is attempted and the msr register user privilege bit, msr[pr], is set. in the 603, this exception is generated for mtspr or mfspr with an invalid spr ?ld if spr[0] = 1 and msr[pr] = 1. this may not be true for all powerpc processors. trap? trap type program exception is generated when any of the conditions speci?d in a trap instruction is met. floating-point unavailable 00800 a ?ating-point unavailable exception is caused by an attempt to execute a ?ating-point instruction (including ?ating-point load, store, and move instructions) when the ?ating- point available bit is disabled, (msr[fp] = 0). decrementer 00900 the decrementer exception occurs when the most signi?ant bit of the decrementer (dec) register transitions from 0 to 1. must also be enabled with the msr[ee] bit. reserved 00a00?0bff system call 00c00 a system call exception occurs when a system call ( sc ) instruction is executed. trace 00d00 a trace exception is taken when msr[se] =1 or when the currently completing instruction is a branch and msr[be] =1. reserved 00e00 the 603 does not generate an exception to this vector. other powerpc processors may use this vector for ?ating-point assist exceptions. reserved 00e10?0fff instruction translation miss 01000 an instruction translation miss exception is caused when an effective address for an instruction fetch cannot be translated by the itlb. data load translation miss 01100 a data load translation miss exception is caused when an effective address for a data load operation cannot be translated by the dtlb. data store translation miss 01200 a data store translation miss exception is caused when an effective address for a data store operation cannot be translated by the dtlb; or where a dtlb hit occurs, and the change bit in the pte must be set due to a data store operation. instruction address breakpoint 01300 an instruction address breakpoint exception occurs when the address (bits 0?29) in the iabr matches the next instruction to complete in the completion unit, and the iabr enable bit (bit 30) is set to 1. table 2. exceptions and conditions (continued) exception type vector offset (hex) causing conditions powerpc 603 risc microprocessor technical summary 23 3.6 memory management the following subsections describe the memory management features of the powerpc architecture, and the 603 implementation, respectively. 3.6.1 powerpc memory management the primary functions of the mmu are to translate logical (effective) addresses to physical addresses for memory accesses, i/o accesses (most i/o accesses are assumed to be memory-mapped), and direct-store interface accesses, and to provide access protection on blocks and pages of memory. there are three types of accesses generated by the 603 that require address translation?instruction accesses, data accesses to memory generated by load and store instructions, and direct-store interface accesses generated by load and store instructions. the powerpc mmu and exception model support demand-paged virtual memory. virtual memory management permits execution of programs larger than the size of physical memory; demand-paged implies that individual pages are loaded into physical memory from system memory only when they are ?st accessed by an executing program. the hashed page table is a variable-sized data structure that de?es the mapping between virtual page numbers and physical page numbers. the page table size is a power of 2, and its starting address is a multiple of its size. the page table contains a number of page table entry groups (ptegs). a pteg contains eight page table entries (ptes) of eight bytes each; therefore, each pteg is 64 bytes long. pteg addresses are entry points for table search operations. address translations are enabled by setting bits in the msr?sr[ir] enables instruction address translations and msr[dr] enables data address translations. 3.6.2 powerpc 603 microprocessor memory management the instruction and data memory management units in the 603 provide 4 gbytes of logical address space accessible to supervisor and user programs with a 4-kbyte page size and 256-mbyte segment size. block sizes range from 128 kbyte to 256 mbyte and are software selectable. in addition, the 603 uses an interim 52-bit virtual address and hashed page tables for generating 32-bit physical addresses. the mmus in the 603 rely on the exception processing mechanism for the implementation of the paged virtual memory environment and for enforcing protection of designated memory areas. instruction and data tlbs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in the event of a tlb hit. a tlb is a cache of the most recently used page table entries. software is responsible for maintaining the consistency of the tlb with memory. the 603 s tlbs are 64-entry, two-way set-associative caches that contain instruction and data address translations. the 603 provides hardware assist for software table search operations through the hashed page table on tlb misses. supervisor software can invalidate tlb entries selectively. system management interrupt 01400 a system management interrupt is caused when msr[ee] =1 and the smi input signal is asserted. reserved 01500?2fff table 2. exceptions and conditions (continued) exception type vector offset (hex) causing conditions 24 powerpc 603 risc microprocessor technical summary the 603 also provides independent four-entry bat arrays for instructions and data that maintain address translations for blocks of memory. these entries de?e blocks that can vary from 128 kbytes to 256 mbytes. the bat arrays are maintained by system software. as speci?d by the powerpc architecture, the hashed page table is a variable-sized data structure that de?es the mapping between virtual page numbers and physical page numbers. the page table size is a power of 2, and its starting address is a multiple of its size. also as speci?d by the powerpc architecture, the page table contains a number of page table entry groups (ptegs). a pteg contains eight page table entries (ptes) of eight bytes each; therefore, each pteg is 64 bytes long. pteg addresses are entry points for table search operations. 3.7 instruction timing the 603 is a pipelined superscalar processor. a pipelined processor is one in which the processing of an instruction is reduced into discrete stages. because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of an execution unit. for example, after an instruction completes the decode stage, it can pass on to the next stage, while the subsequent instruction can advance into the decode stage. this improves the throughput of the instruction ?w. for example, it may take three cycles for a ?ating-point instruction to complete, but if there are no stalls in the ?ating-point pipeline, a series of ?ating-point instructions can have a throughput of one instruction per cycle. the instruction pipeline in the 603 has four major pipeline stages, described as follows: the fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next instruction fetch. additionally, the bpu decodes branches during the fetch stage and folds out branch instructions before the dispatch stage if possible. the dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction fetch stage, and determining which of the instructions are eligible to be dispatched in the current cycle. in addition, the source operands of the instructions are read from the appropriate register ?e and dispatched with the instruction to the execute pipeline stage. at the end of the dispatch pipeline stage, the dispatched instructions and their operands are latched by the appropriate execution unit. during the execute pipeline stage each execution unit that has an executable instruction executes the selected instruction (perhaps over multiple cycles), writes the instruction's result into the appropriate rename register, and noti?s the completion stage that the instruction has ?ished execution. in the case of an internal exception, the execution unit reports the exception to the completion/writeback pipeline stage and discontinues instruction execution until the exception is handled. the exception is not signaled until that instruction is the next to be completed. execution of most ?ating-point instructions is pipelined within the fpu allowing up to three instructions to be executing in the fpu concurrently. the pipeline stages for the ?ating-point unit are multiply, add, and round-convert. execution of most load/store instructions is also pipelined. the load/store unit has two pipeline stages. the ?st stage is for effective address calculation and mmu translation and the second stage is for accessing the data in the cache. the complete/writeback pipeline stage maintains the correct architectural machine state and transfers the contents of the rename registers to the gprs and fprs as instructions are retired. if the completion logic detects an instruction causing an exception, all following instructions are cancelled, their execution results in rename registers are discarded, and instructions are fetched from the correct instruction stream. a superscalar processor is one that issues multiple independent instructions into multiple pipelines allowing instructions to execute in parallel. the 603 has ?e independent execution units, one each for integer instructions, ?ating-point instructions, branch instructions, load/store instructions, and system register instructions. the iu and the fpu each have dedicated register ?es for maintaining operands (gprs and powerpc 603 risc microprocessor technical summary 25 fprs, respectively), allowing integer calculations and ?ating-point calculations to occur simultaneously without interference. because the powerpc architecture can be applied to such a wide variety of implementations, instruction timing among various powerpc processors varies accordingly. 3.8 system interface the system interface is speci? for each powerpc microprocessor implementation. the 603 provides a versatile system interface that allows for a wide range of implementations. the interface includes a 32-bit address bus, a 32- or 64-bit data bus, and 56 control and information signals (see figure 4). the system interface allows for address-only transactions as well as address and data transactions. the 603 control and information signals include the address arbitration, address start, address transfer, transfer attribute, address termination, data arbitration, data transfer, data termination, and processor state signals. test and control signals provide diagnostics for selected internal circuits. figure 4. system interface the system interface supports bus pipelining, which allows the address tenure of one transaction to overlap the data tenure of another. the extent of the pipelining depends on external arbitration and control circuitry. similarly, the 603 supports split-bus transactions for systems with multiple potential bus masters?ne device can have mastership of the address bus while another has mastership of the data bus. allowing multiple bus transactions to occur simultaneously increases the available bus bandwidth for other activity and as a result, improves performance. the 603 supports multiple masters through a bus arbitration scheme that allows various devices to compete for the shared bus resource. the arbitration logic can implement priority protocols, such as fairness, and can park masters to avoid arbitration overhead. the mei protocol ensures coherency among multiple devices and system memory. also, the 603's on-chip caches and tlbs and optional second-level caches can be controlled externally. the 603 s clocking structure allows the bus to operate at integer multiples of the processor cycle time. the following sections describe the 603 bus support for memory and direct-store interface operations. note that some signals perform different functions depending upon the addressing protocol used. 3.8.1 memory accesses the 603 s data bus is con?ured at power-up to either a 32- or 64-bit width. when the 603 is con?ured with a 32-bit data bus, memory accesses allow transfer sizes of 8, 16, 24, or 32 bits in one bus clock cycle. data transfers occur in either single-beat transactions, or two-beat or eight-beat burst transactions, with a 603 address address arbitration address start address transfer transfer attribute address termination clocks data data arbitration data transfer data termination processor state test and control +3.3 v 26 powerpc 603 risc microprocessor technical summary single-beat transaction transferring as many as 32 bits. single- or double-beat transactions are caused by noncached accesses that access memory directly (that is, reads and writes when caching is disabled, cache- inhibited accesses, and stores in write-through mode). eight-beat burst transactions, which always transfer an entire cache line (32 bytes), are initiated when a line is read from or written to memory. when the 603 is con?ured with a 64-bit data bus, memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus clock cycle. data transfers occur in either single-beat transactions or four- beat burst transactions. single-beat transactions are caused by noncached accesses that access memory directly (that is, reads and writes when caching is disabled, cache-inhibited accesses, and stores in write- through mode). four-beat burst transactions, which always transfer an entire cache line (32 bytes), are initiated when a line is read from or written to memory. 3.8.2 direct-store interface operations both memory and i/o accesses can use the same bus transfer protocols. the 603 also has the ability to de?e memory areas as direct-store interface areas. accesses to the direct-store interface rede?e the function of some of the address transfer and transfer attribute signals and add control to facilitate transfers between the 603 and speci? i/o devices. direct-store interface transactions provide multiple transaction operations for variably-sized data transfers (1 to 128 bytes) and support a split request/response protocol. the distinction between the two types of transfers is made with separate signals?s for memory-mapped accesses and xa ts for direct-store interface accesses. 3.8.3 powerpc 603 microprocessor signals the 603 signals are grouped as follows: address arbitration signals?he 603 uses these signals to arbitrate for address bus mastership. address transfer start signals?hese signals indicate that a bus master has begun a transaction on the address bus. address transfer signals?hese signals, which consist of the address bus, address parity, and address parity error signals, are used to transfer the address and to ensure the integrity of the transfer. transfer attribute signals?hese signals provide information about the type of transfer, such as the transfer size and whether the transaction is bursted, write-through, or cache-inhibited. address transfer termination signals?hese signals are used to acknowledge the end of the address phase of the transaction. they also indicate whether a condition exists that requires the address phase to be repeated. data arbitration signals?he 603 uses these signals to arbitrate for data bus mastership. data transfer signals?hese signals, which consist of the data bus, data parity, and data parity error signals, are used to transfer the data and to ensure the integrity of the transfer. data transfer termination signals?ata termination signals are required after each data beat in a data transfer. in a single-beat transaction, the data termination signals also indicate the end of the tenure, while in burst accesses, the data termination signals apply to individual beats and indicate the end of the tenure only after the ?al data beat. they also indicate whether a condition exists that requires the data phase to be repeated. system status signals?hese signals include the interrupt signal, checkstop signals, and both soft- and hard-reset signals. these signals are used to interrupt and, under various conditions, to reset the processor. processor state signals?hese signals indicate the state of the reservation coherency bit, enable the time base, provide machine quiesce control, and cause a machine halt on execution of a tlbsync instruction. powerpc 603 risc microprocessor technical summary 27 ieee 1149.1(jtag)/cop interface signals?he ieee 1149.1 test unit and the common on-chip processor (cop) unit are accessed through a shared set of input, output, and clocking signals. the ieee 1149.1/cop interface provides a means for boundary scan testing and internal debugging of the 603. test interface signals?hese signals are used for production testing. clock signals?hese signals determine the system clock frequency. these signals can also be used to synchronize multiprocessor systems. note a bar over a signal name indicates that the signal is active low?or example, ar tr y (address retry) and ts (transfer start). active-low signals are referred to as asserted (active) when they are low and negated when they are high. signals that are not active-low, such as ap0?p3 (address bus parity signals) and tt0?t4 (transfer type signals) are referred to as asserted when they are high and negated when they are low. 3.8.4 signal con?uration figure 5 illustrates the 603's logical pin con?uration, showing how the signals are grouped. figure 5. powerpc 603 microprocessor signal groups 1 1 1 1 1 3 2 4 1 5 1 3 1 1 1 1 2 1 1 1 1 1 1 6 4 8 1 1 1 1 1 2 1 2 2 1 2 1 1 5 603 dbg dbwo dbb dh0?h31, dl0?l31 dp0?p7 dpe dbdis ta drtry tea int , smi mcp ckstp , checkstop hreset , sreset rsrv qreq , qack tben tlbisync trst , tck , tms , tdi , td0 address arbitration address start address bus transfer attribute address termination clocks data arbitration data transfer data termination interrupts checkstops reset processor status jtag/cop interface +3.3 v gbl br bg abb ts xats a0?31 ap0?p3 ape tt0?t4 tbst tsiz0?siz2 ci wt cse tc0?c1 aack artry sysclk clk_out pll_cfg0 ?pllcfg3 information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. there are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the information in this document. the powerpc 603 microprocessor embodies the intellectual property of ibm and of motorola. however, neither party assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party. neither party is to be considered an agent or representative of the other party, and neither has granted any right or authority to the other to assume or create any express or implied obligations on its behalf. information such as errata sheets and data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the microprocessor may vary as between ibm and motorola. accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. both ibm and motorola reserve the right to modify this manual and/or any of the products as described herein without further notice. nothing in this manual, nor in any of the errata sheets, data sheets, and other supporting documentation, shall be interpreted as conveying an express or implied warranty, representation, or guarantee regarding the suitability of the products for any particular purpose. the parties do not assume any liability or obligation for damages of any kind arising out of the application or use of these materials. any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. in the absence of such an agreement, no liability is assumed by the marketing party for any damages, actual or otherwise. ?ypical parameters can and do vary in different applications. all operating parameters, including ?ypicals, must be validated for each customer application by customer s technical experts. neither ibm nor motorola convey any license under their respective intellectual property rights nor the rights of others. the products described in this manual are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold ibm and motorola and their respective of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola or ibm was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. ibm is a registered trademark of ibm corp. , , powerpc, powerpc architecture, power architecture, powerpc 603, and powerpc 601 are trademarks of international business machines corp. used by motorola under license from ibm corp. motorola literature distribution centers: usa: motorola literature distribution, p.o. box 20912, phoenix, arizona 85036. europe: motorola ltd., european literature centre, 88 tanners drive, blakelands, milton keynes, mk14 5bp, england. japan: nippon motorola ltd., 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd., silicon harbour centre, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. technical information : motorola inc. semiconductor products sector technical responsiveness center; (800) 521-6274. document comments : fax (512) 891-2638, attn: risc applications engineering. ibm microelectronics: usa: ibm microelectronics, mail stop a25/862-1, powerpc marketing, 1000 river street, essex junction, vt 05452-4299; tel.: (800) powerpc [(800) 769-3772]; fax (800) powerfax [(800) 769-3732]. europe: ibm microelectronics, powerpc marketing, dept. 1045, 224 boulevard j.f. kennedy, 91105 corbeil-essonnes cedex, france; tel. (33) 1-60-88 5167; fax (33) 1-60-88 4920. japan: ibm microelectronics, powerpc marketing, dept., r0260, 800 ichimiyake, yasu-cho, yasu-gun, shinga-ken, japan 520-23; tel. (81) 775-87-4745; fax (81) 775-87-4735. |
Price & Availability of MPC603DR3
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |